For the last few weeks I’ve been working on the design of a video card for my 68020 based computer, MIDI020.
Though it will principally be a video card, it makes sense to include sound generation functionality as well, and I’ve been looking at a couple of approaches to this. Though I could look at using an FM synthesis IC, like the OPL2 I’ve previously played with, I continue to think PCM playback is the way to go.
My initial design for this was as an extension of MAXI000‘s SPI DACs. MAXI000 uses two MCP4902 (PDF) dual channel 8 bit DACs to drive a stereo 3.5mm jack. As described in a previous post I had this driven directly from the 68000, with timing done with a simple delay loop. I’ve since extended this with playback via Beta’s local memory, usually used by the video display. In essence the PCM data’s start address, length and playback rate can be written into registers and playback completed without any further processor interactions.
It worked fairly well. I even recorded a musical scale played with a piano sample recording:
One flaw with the current hardware design is the use of one channel to set the volume of the playback; the volume channel is used as the reference of the output channel. The inspiration for this came from Paula, the Amiga‘s sound controller, but since the volume value sets the reference on the main output channel the output is scaled between 0V and 5V but it is not centered about 2.5V. A very quiet sample will playback between 0V and just over 0V, and a loud sample will play back between 0V and 5V, and switching from quiet to loud will generate it’s own transition (“pop”) on the output.
There are most likely approaches to solving this using a more sophisticated output stage, ie. operational amplifiers, but instead I’ve chosen an alternative approach for PCM sound output on the video/sound card: an I2S DAC IC with built in line drivers.
I2S is a signalling standard designed as a digital sound equivalent to I2C: a way to transfer digital audio data from IC to IC in audio equipment, like CD players.
The DAC I’ve chosen is the UDA1334ATS (PDF). It’s a pretty straightforward part: I2S signals go in one side and an audio signal, at line out levels, comes out the other side.
Here is the schematic sheet for this section of the video and sound expansion board:
This schematic is a mixture of information from the datasheet and from an Adafruit breakout board for this part.
Each I2S pin is attached directly to the FPGA. One thing this part does not have is a volume control, but I’m hoping I can do volume type data modifications inside the FPGA. In any case, sound is just a “nice to have” for this board; the real fun is in the video portion.
As I’ve previously stated, a Cyclone II (PDF) FPGA will be used for driving the video generation, and for interfacing to the I2S DAC. The particular one I’ve chosen, a EP2C8Q208I8N (PDF), has the following features:
- 208 pins in QFP, 138 available for IO
- 8,256 Logic Elements
- 165,888 RAM bits (20.25KByte)
- 13 multipliers
- 2 Phase-locked Loops
The latter two are new, relative to the Flex 10K (PDF), though my softcore project made use of both when implemented in my DE2-115 development board. The PLL is particularly useful for a video controller as it should allow alternative screen modes to be used, where the pixel clock is generated by the PLL using a master clock as a source.
The schematic for the video functionality is an extension of my previous efforts with the MAXI000 board, but there are a few surprises. First up the top level:
But nothing at all surprising here, except that the SDA and SCL pins are around the right way, unlike every previous expansion board I’ve designed. As a reminder, the AT24C64 (PDF) is an I2C EEPROM which will hold various settings information which could, in the future, be used for the automatic configuration of address information, interrupts and other resources the card needs.
The power section contains the power connections for the FPGA (there are far too many pins to fit everything on a single sheet) and its regulators. It needs two power rails:
- 1.2V is used for the internal logic, and the PLLs.
- 3.3V is used, in this design, for IO.
Two linear regulators are used from the AZ117 (PDF) series. These are 1A parts in a SOT-223 package. A probe point is used so I will be able to confirm the output level with the multimeter and, for good measure, an LED is also attached to the power rail. The 3.3VDAC rail is used by the DAC section, and is the same as the 3.3V line after filtering with a bead.
Next, the main FPGA section. The connections break down as follows:
- Processor address and data buses (LA0 to 21 and LD16 to 31) – these are level shifted from 5V down to 3.3V
- Processor control inputs (/LREAD, /LWRITE, etc) – also level shifted, hence the “L” prefix
- Processor control outputs (/LINT, /LBERR, etc)
- Video memory address and databuses (VA0 to 19 and VD0 to 15)
- Video memory control, including byte select (/VREAD, /VWRITE, /VUCS and /VLCS)
- Red, Green and Blue level, 8 bits each
- Horizontal and Vertical sync
- Blanking and clock outputs for the DAC
- I2S signals, as previously described
- Clocks: Pixel clock from this board, and master clock and processor clock from the MIDI020 board (the latter two are level shifted)
- A pair of additional config lines from the configuration flash (CFGASDI and /CFGCS)
- An LED driving pin, just because they are always useful
- 4 unused pins
In terms of the video clock, I will probably stick with a 25.175MHz oscillator can, though with the PLL in the FPGA I could produce this clock on demand, in the same way as I did within my softcore experiments running on the DE2-115 board.
There were four unused pins, so I attached them to a header. They might be useful for monitoring internal signals, or perhaps I could use them to hook up ICs to an SPI bus.
Next, the FPGA configuration section. This is actually simpler then with the Flex10K, since the configuration device is not on the JTAG chain. Instead, like the Cyclone IV on the DE2-115, the configuration device is programmed by loading a special “sideways” programmer design into the FPGA which then relays the data from the PC into the configuration flash.
The configuration flash in question is an EPCQ4 (PDF), which is a 4Mbit device.
Next the video memory and the DAC.
The video memory is a single part, an IS61WV1024 (PDF) 1M by 16 SRAM, which like most of the other parts on this boards, runs at 3.3V. The upper and lower halves of the memory array can be accessed independently via the /LB and /UB pins.
The DAC is probably the most interesting part of the whole board: since I had so many pins to utilise, I thought I might as well use a proper DAC IC, the ADV7123 (PDF). This is the same part as used on the DE2-115, and the Amiga 1200, so I have some familiarity with it. It is a 3 x 10 bit DAC, but only the upper 8 bits on each channel are used. This schematic is largely borrowed from the DE2-115.
Finally, the level shifters. Shifters are needed for the processor data bus (2 by 8 bits), processor address bus (3 by 8 bits, though the top bits on the top shifter are used for the clocks), and processor control signals. For the processor control signals, separate in and out shifters are required since a shifter must entirely be given up to shifting in one direction.
I’m not sure if it’s required, but the 3.3V and 5V lines are both decoupled. The 8 bit bidirectional shifter used is the SN74LVC8T245 (PDF).
Next up, the PCB design.
A key step to reducing board complexity, when using FPGAs, is to use the best FPGA pin for a particular connection to a particular part. A case in point is when an FPGA is joined to memories: memory ICs typically have a fairly random pin arrangement, and vias and long winding traces can almost entirely be removed if the FPGA pinning matches these connections. This board did this extensively for pretty much of all of the FPGA IO pins, and the result is a board I’m rather pleased with:
Internally, there is a 0V power plane. The second internal layer (yellow in the above picture) is used for the 3.3V and 1.2V power connections to the FPGA, as well as the 3.3VDAC power rail shared by the video and audio DACs.
Here’s the obligatory 3D view:
It’s even more clear from this picture how much the 208 pin FPGA dominates this board. I’m using large tantalum capacitors as alternatives to the usual electrolytics to save space, though the board does contain a single one (220uF) decoupling the 5V supply in the bottom left.
There are many passive components on the back of the board, which is why the front side looks relatively “clean”:
All in all I’m pretty happy with the PCB design for this board. I only hopes it works as well as it looks. Another thing of note is that 8 mil wide traces were used instead of 6 mil, which all my 68000 boards have so far used. This was possible because there are no 100 mil spaced PLCC or PGA pins to route between, which is usually why my other boards require the thinner 6 mil traces.
This board has been ordered from my usual supplier, JLCPCB. As well as this board, I also ordered updated versions of the previously described Ethernet+Printer+Joystick board, and the Test+SRAM board. It is not really worth going over those again, but suffice to say after “test fitting” parts on a board paper print out I noticed several more footprint errors, beyond the initial show stopper with the RTL8019 (PDF) footprint.
To build the video board I still require a few parts from mouser.com. This includes the critical 3.3V pixel clock oscillator. When placing this order, I will also order some parts I’ll need for a future MAXI030 board, which will feature a 68030. I’m jumping ahead of myself, but since it’s so much fun thinking about future projects…