A 16 bit softcore processor: Introduction

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During my A-level electronics class I studied many interesting topics including:

The 6502 assembly programming was particularly interesting because it was hands on using some teaching boards that consisted of a 6502, a tiny amount of SRAM, some IO devices, and a debug monitor which used a hex keypad and 7 segment displays. In the classroom we hand assembled simple programs to play tunes and keyed them in using the hex keypad. It was a lot of fun, though even then (1992 or so) the 6502 was long in the tooth. A few years ago I tracked down the board we used via the clever folks at 6502.org:

Another thing about my A-level electronics course is that the exam used a paper design of a very simple 8 bit CPU. The tiny instruction set was presented and using this information the exam required you to write some simple programs. What struck me at the time is that someone had simply dreamed up this hypothetical processor. It didn’t exist yet you could write programs and run them, by hand, on it. Such concepts were totally alien to me: I saw processors and computers only as physical things; programs as things that ran on real computers. I was so intrigued by these new ideas I wrote a simulator in AMOS Basic on my Amiga for this imaginary processor and used it to write more programs. I even extended the design by adding more instructions. Since then the idea of designing and implementing my own processor has always been with me.

So now, as a break from working on my MAXI000 board, I thought it would be fun to finally do something with this “itch”.

Obviously I will run the design in an FPGA. Whilst it would be interesting to tackle this project with 74 series parts, it would be a crippling slow build, especially because I do not have a concrete design in mind at the outset and will instead be evolving through the design as I go.

I also don’t have a specific FPGA in mind.

This leads to an interesting observation: it might be possible to run up a processor within the Alpha FPGA on the MAXI000 board.

The MAXI000 board contains everything a simple processor could need: ample and easy to use SRAM and ROM (Flash), UART ports, and even video output. The 68000 could be locked in the halted state with busses tristated, with a softcore processor in Alpha able to use anything on the buses, however wide they might be.

The only problem with this is the amount of logic resources available in an EPF10K20 (PDF). I’m pretty sure a simple 8 bit processor could fit though.

There are ample development boards available with very large, by the standards of the FPGAs I’ve been using for my 6809 and 68000 projects, parts available for under £100. In fact I’ve had one in my parts drawer for a few years. So far its not even been powered up, however it appears to be ideal for this project. Here it is:

Hardware on the board includes:

The board is an Ebay purchase, marked as a Zrtech Cyclone IV. Beside the choice of SDRAM it makes a pretty cool target for a small softcore. Looking at the datasheet the EP4CE6E22C8 has around six times the logic elements of the EPF10K20, however it also has around 40 times the memory bits. It also has multipliers (PDF), differential IO pins, and Phase Lock Loops not present in the Flex10K parts. Presumably only the multipliers would be useful in a processor.

With a possible board in mind, the next step was and is to outline the capabilities for a simple processor.

As this is my first project of this sort the bar is fairly low. This will not be a stellar performer, nor do I expect it to be easy to program for. It’s main purpose is really to teach me more about Programmable Logic.

The basic capabilities in mind are:

  • 16 bit address and databuses
  • 16 bit instruction word
  • Some instructions have one following 16 bit quantity, an immediate value
  • 8 x 16 bit general purpose registers
  • 16 bit Program Counter
  • Load and Store instructions using:
    • Immediate value (Load only)
    • Immediate memory address
    • Register holding an address
    • Register holding an address, with an immediate displacement
  • Status bits: Carry, Zero, Negative – updated after an ALU operation
  • ALU operations include: add, add with carry, subtract, subtract with carry,  increment, decrement, and, or, xor, not, etc
  • ALU operations are of the form DEST <= DEST op OPERAND or DEST <= op DEST, where DEST a register and OPERAND is either a register or an immediate 16 bit value
  • Jumps and branches: always or on any combination of flag value, including don’t cares
  • Nop instruction
  • Clear register instruction
  • Call subroutine via jump or branch
  • Push and pop; basic stack operations
  • No microcode; a coded state machine will be used

A current limitation, or rather thing to be worked on later, is interrupts.

The processors native type is 16 bit, that is the ALU understands only 16bit quantities. However loads and stores can also perform 8 bit transfers with either zero or sign extensions. Addresses in the system are byte wide, and the 68000s method of indicating the type of bus transfer is used, namely upper and lower strobes. Word accesses must be properly aligned.

At some point I want to become “bilingual” and teach myself Verilog, but for now I will stick to VHDL for this project.

Unlike much of my previous hacked together VHDL coding, this project is and will be validated with unit tests (test benches) as much as possible. The design will be broken down into entities to aid in this and to keep the bits of functionality independent.

To achieve this, I have decided to switch my ECAD programmable logic work from my Windows 7 VM to my Ububtu desktop, and simultaneously switch to the latest Altera (now Intel) Quartus software since, for this project at least, I don’t need to work with a version that supports the Flex10Ks used in my 6809 and 68000 projects. As I’d previously found with my brief exploits in writing test beches, Quartus ships with MentorGraphics‘s ModelSim which can be driven from the command line, and should work well.

The processor design uses as inspiration many sources including Ben Eater’s and James Sharman’s excellent breadboard computers, as well as some tutorials on the subject. In addition I have watched some lectures on the design of the MIPS processor and drew some inspiration from there. The VHDL coding is and will continue to be all original work however.

The next blog post will discuss the design in detail.

1 thought on “A 16 bit softcore processor: Introduction

  1. Doug Rice

    I found your blog with the zrtech wxeda board.
    Not too much on the web for this board.
    Grant Searle’s multicomp FPGA is worth a read.
    Doug Gilland has a port for this board so you can run z80 6502 or 6809 code.

    I had a happy day or two with the built in logic analyser and workout out how to upload code without a rebuild of the .sof file.

    I have been trying to learn VHDL with GHDL.

    Thanks for your blog!

    Regards Doug.


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