The IO board for the MINI000, outlined in the last post, has been designed and the PCB, pending some final checks, will soon be ordered from the allpcb.com PCB house in China.

A few ICs have not made it. I’d hoped to include a MC68230 (PDF) but as they are available only in DIP48, there’s just not enough room for one. Plus the DB25 for the parallel port would take up a considerable amount of room on the edge of the board.

I could probably have squeezed on an addressable latch and DB9 Atari joystick connector, but it seemed a bit pointless. All told, I’ve settled on an EPF10K10 (PDF)  for the VGA output, a 68681 (PDF) for the keyboard interfacing DUART, an IDE IDC header, and an OPL2 (AKA YM3812 ).

Some parts of the board were prototyped, though not all. One part that wasn’t is the 68681 DUART. The IC I have was made by Philips; it seems that Motorola did not make this part in PLCC, and I was keen to use this in PLCC44 instead of the more common (for this part) DIP40 to save board space. I chose not to bother prototyping it as the IC is designed to work with the 68000 series and is well documented with example circuits. One channel is routed to an RJ10 4 way socket. This will be used to attach the external keyboard, using the same type of curly cable as used on telephone handsets. The other channel has a header attached, just for testing. Finally, the general purpose IOs are also hooked up: the OP0 output to an LED, whilst the 6 inputs are hardwired to a particular bit pattern. Again this is just so I can test out these IC features.

Here is the schematic for this section:

The EPF10K10 in PLCC84 is hooked up much as it was in the VGA breadboard rig, with two differences.

Firstly 3 IDT71256SA (PDF) 12nS 32KByte SRAMs are attached. This will give the FPGA access to 96KByte of video memory, and gives enough memory for a 4 colour bitmap display at 640×480, or alternatively 256 colours at 320×240, using doubled up pixels.

Secondly I have added a 3 bit resistor DAC for each of the red, green and blue outputs. This will allow 8 levels of intensity for each colour, giving 512 possible colours. It’s likely that I’ll use the FPGA RAM bits for holding the palette.

The board contains provision, via a jumper, for either routing the MPU clock, generate by the oscillator on the MINI000 board, to the FPGA or for generating the MPU clock from the FPGA and feeding it to the MINI000 board. This will allow me to experiment with driving the MPU with a clock which is a fraction of the VGA pixel clock. One of my biggest worries with this VGA controller is whether I can solve the problems with writes through to the video memory getting corrupted and this gives me some flexibility to experiment with different approaches.

The schematic for the video section:

Notice that the FPGA has a /DTACK output and can also generate interrupts, though this is only their current use and it is not at all fixed, these signals being routed to the CPLD in the MINI000 board and they could be used for other purposes.

The board also contains an IDE 40 pin IDC header. This part was prototyped:

Unfortunately I forgot to take a picture of the breadboard attached to the MINI000 board.

The hookup is basically identical to the one used previously on my 6809 boards, except that the whole of the 16 bit databus can now be attached directly to the MPU. Because IDE is essentially an extension of ISA, the bus is little endian. To avoid having to byte swap in code every word read or written, the bus is swapped in the wiring. I found out about this trick looking at the Amiga 1200 schematic.

Some monitor commands were written to read and write sectors, and perform the IDENTIFY command. Once again I neglected to take any screenshots. I did however measure the transfer rate using the logic analyser and was pleased to see, with only PIO used to pull off the sectors, that a transfer rate of just over 1MB a second has been achieved.

For completeness here is the schematic for the IDE portion:

Finally I have breadboarded up a YM3812 (OPL2) FM synthesizer, as used on the MAXI09. It works well, though it requires wait states and pauses between register writes, due to the relative speed of the 68000. Here’s a picture of the breadboard setup, which is basically identical to the one made previously for the MAXI09:

I am not completely set on using the OPL2 in a larger 68000 board; a hypothetical MAXI000. It’s makes nice sounds, but it also has the feeling of being an 8 bit part.

Once again for completeness, here is the schematic. Note that this time a 74HC590 (PDF) 8 bit counter is used to divide down the 14.3181 Mhz NTSC clock. This dividing down is done with a discrete counter only because the EPF10K10 has no free pins:

Finally, the decoupling caps, power LED, power related connections and expansion connector:

The “not connected” connections to the right of the expansion connector are there only to satisfy the Design Rule Checker; these pins are connected to the MINI000 in the “real world” but since this schematic only covers the IO board, these connections need to be “cut off” otherwise the DRC will flag them as being not connected to a driver.

After all the prototyping and producing a schematic, the last thing to do was to layout the PCB. As per the MINI000, the PCB is a 4 layer board with internal power planes.

This PCB layout process was a little different to previous boards because placement of the connectors (eg. the DB15 for the VGA port) was essential to do correctly because the board is a daughterboard for the MINI000, sitting below it.

The first step was to position the two 40 pin PCB sockets for the expansion connector, and the two 4 pin PCB sockets for power. These connections will be used to join the IO board to the rest of the computer. The board itself can only be as big as the internal area within these PCB sockets, an area about 4 inches square.

After those parts had been placed, the next job was to place the connectors: the DB15, RJ10, the 3.5mm socket for the OPL2 and the IDE header. I chose to place the first three along the left hand edge. The right hand edge is taken up by the IDE connector; this placement is largely dictated by the Dual RJ45 sockets used for the DUART on the MINI000, which would get in the way of connectors on the board above.

Placing the rest of the components was set, for the most part, the prior placing of the connectors, eg. the EPF10K10 was placed near the DB15. I managed to squeeze the resistor DAC, consisting of 18 upright resistors into a tiny space between the DB15 and the FPGA. Unlike in previous boards, I tweaked the configuration of the FPGA pins to achieve a better layout changing, for example, the position of the 9 (Red, Green and Blue times 3 bits) pins to be closer to the RGB resistor DAC.

One thing I realised when I started the layout process is that the JTAG chain could have been extended across the expansion connector. This would have meant that I wouldn’t have needed a JTAG header on the IO board. Not a big deal, but moving the programmer between the MINI000 board and the IO board to program each one is going to be a little annoying.

I managed to route the board with only a little fuss, probably helped by the careful placing of the parts. Trace and via sizes are the same as the MINI000: 6mil wide traces with 6 mil clearances. I managed to avoid routing 3 traces between 2 100mil spaced pads, which is an improvement on the MINI000. The number of vias is still fairly high, but I’m pretty happy with the overall layout:

(The Vcc and GND planes are not worth showing.)

The obligatory 3D view:

I even added the PCB sockets to the expansion and power connectors, so here is a view from the bottom of the board:

One thing which would be great is the ability to export 3D models of the completed MINI000 and this new board and do a “dry run” fit using these models to check that they will go together nicely. This would be useful for checking that the connectors on the IO board are not obstructed by any part of the MINI000 board below. Without this functionality in the software, I took a low-tech solution: I printed both boards designs out on paper, held the two sheets up to a bright light and lined up the expansion connector. This revealed a concern with the DB15 being blocked by the JTAG header on the MINI000, but I think it will be alright.

As I mentioned at the start of this post, I still have to do some final checking before ordering the board. Hopefully I’ll have the fabricated boards in my hands soon…