Designing a 68000 SBC

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I have decided to be a little brave and have opted to build a 68000 SBC instead of one based off a 68008. Specification wise it is similar to the 68020 design:

  • 68000 clocked at 16MHz
  • 1MB static RAM (2 x AS6C4008 (PDF))
  • 64KB EEPROM (2 x AT28C256 (PDF))
  • DUART (XR88C681 or, in its place, a SC2681 (PDF)))
  • Expansion connector

Both memories will be 16 bits wide, making this a true 16 bit computer. The glue logic will be supplied by an EPM7128S (PDF)  in PLCC84, the same part I planned to use in my 68020 SBC. Here is the MPU, CPLD and expansion connector schematic section:

I have both the gigantic DIP64 (harvested from an Amiga 500) and PLCC68 versions of the 68000 available. Because of wanting to keep the size of the board down, even though it will make routing harder, I’ve gone for the PLCC version. Also worthy of note, it is the 68HC000 – the low power CMOS derivative.

All MPU pins are exposed on the expansion connector. It will use two 40-way pin headers. This will allow me to experiment with an external bus master, amongst other things, but routing the board will prove to be a challenge!

All the control signals from the MPU are also routed to the CPLD meaning I can experiment with some of the more interesting ones like the FCn (Function Code) pins. The expansion connector also has 14 unallocated CPLD pins. These will be used for chip selects, interrupt pins etc.

Finally, the CPLD will be addressable (8 bits wide) from the MPU. This will be used for configuring interrupt routing, turning on the LED, sounding the buzzer etc.

Next up, the memory section:

Absolutely nothing to say about this, except that unlike in the 68020 even the EEPROM must be 16 bits wide.


Because the SC2681 lacks a dedicated CTS pin on its DIP28 package variant, there are no hardware handshaking lines available. Therefore the RS232 level shifter is a dual channel MAX232 instead of the quad channel MAX238 I’ve previously used. The main reason for theses choices is the availability of parts to hand.

Also, note how there is no A0. The 68000, unlike the 68008 does not have one. Instead the memory and peripheral ICs must be selected out of the /UDS and /LDS upper and lower data strobes. In the case of peripheral ICs, instead of manufacturing an A0 signal, the byte-wide registers (all of them within an IC) are simply addressed on even (or odd) addresses.

Power and reset generation:

I’ve gone back to using a DS1813 for power on reset signalling. The non-inverted signal, which must be generated anyway, is used by the DUART. Power will be provided by the potted switching regulator used by the MAXI09 board.

This board’s name: MINI000. It might not make any sense, but it is kind of consistent with the MAXI09.

After finalising the schematic it was time for some PCB routing.

In short, after about 12 hours work, it is done. I am not amazingly happy with the number of vias used but the board is at least pretty compact, being not much bigger then the previous 6809 SBC at 5.85 by 4.8 inches (148.6 by 122 mm). I’m especially happy to have a fully pinned expansion connector on the board which will allow me to play with all kinds of cool things on some attached breadboard:

  • ICs like the 6522. It’s unclear to me if I must use the 68000’s synchronous bus pins for these older parts or whether it is possible to use the standard asynchronous bus protocol.
  • I’d like to experiment with attaching DRAM. These would allow me to attach “massive” memories (certainly enough to fill the 68000s 16MB address space)
  • Compact Flash or perhaps some other form of mass storage.
  • DMA controllers, either my own design or an off the shelf (contemporarily speaking) part.

So there are no real limits; this SBC, assuming I haven’t made a massive mistake somewhere, should be a great step to designing an extremely well spec’d 68020 or even 68030 based computer, in a similar vain to the MAXI09 which I think represents the best possible 8 bit micro.

Back to the PCB design.

Here’s the design as it currently stands, some final tweaks still to do:

The CPLD is at the bottom left. The sheer number of visa continues to be something I’m not happy with, but I think I will have to live with it. One negative against KiCAD is it does not support back annotations properly; it would be nice if the PCB could dictate the pinning on the CPLD and even the expansion connector so the best routes could be used for those parts since the mapping to physical pin in those cases is configurable in the programmable logic.

As before, it should be possible to stack an I/O (or other) board on top. I’m not sure if I’ll ever make such a PCB, as the main use of the expansion connector will be to attach the board to breadboards, but the option is there. I have ensured that no parts which need to be accessible while a daughter board is attached will be hidden by such a board, including the JTAG header and reset button.

Because they are great to look at, here’s a 3D render of the board:

Unfortunately I wasn’t able to locate a model for the dual RJ45 sockets, spoiling the view a little.

After some final tweaking, I will order the board(s) from Total cost should be about US$80, which is stupidly reasonable considering it is a 4 layer board.

While waiting for it to arrive there is Christmas to enjoy, and some VHDL to update. There is also a 68000 machine code monitor to write…

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