An FPGA dev board on breadboard

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In the end I ordered some additional PLCC sockets from the UK and was surprised and happy that they arrived in only a couple of days.

Soldering the sockets was easy, considering the board lacks a solder mask. Possibly the use of some liquid flux helped. I was happy with the result although it is not quite perfect:

The next step was to attach the adapter to the breadboard. This is the setup in the initial configuration, with the FPGA in its 84 pin adapter, flash in its 20 pin adapter, 10 pin IDC socket for the JTAG connection and power adapter. At this stage the FPGA was not wired to receive the design from the flash:

The ribbon connector was for the next step. The first thing to do was to verify that I could program both the flash and the FPGA. After fixing a missing connection everything was fine; the FPGA accepted the design.

The missing connection was the TRST JTAG line. Some programmers support this, some do not. If it is missing it needs to be tied high.

The next step was to verify that the FPGA would implement a design that was programmed into it. The simplest design worth testing is a counter. Just to make it slightly more interesting I made it an up down counter with reset. The counter is clocked via an “external” counter which divides down the 8Mhz can oscillator to make the 8 bit counter’s output changes perceptible. To obtain a 1Hz output from a 8Mhz input, a 23 bit counter is required. The updated breadboard looks like the following:

You can see the can oscillator, two buttons (one for reset and one to make the counter count down) and the 8 LEDs along the top row of the breadboard. The counter worked well, and the VHDL is so trivial it is not worth showing. It was a big relief to see this working. Another nice thing was how quickly the design was downloaded onto the FPGA: only a few milliseconds were needed. The other thing worth noting is that it was still possible to program the flash in this configuration without removing any wires. Indeed, whilst the flash was being updated, the FPGA kept on going.

Of course when power was removed the FPGA lost the design. So the next step was to hook up the serial programming bus between the flash and the FPGA. After a few misswirings were corrected this worked well. I need to get the Analyser on the breadboard to properly time it out, but it appears to, again, take only a few milliseconds after power on for the counter outputs to show at the LEDs. Looking at the breadboard now it is easy to think that this is a lot of components and wires to do the same thing that I had the XC9572 doing a year or so ago. The difference is that the FPGA can hold a design that is many times more complex.

For fun, I also made a 16 bit up down counter with seven segment display. This was based on the previous 8 bit up down counter with display implemented on a CPLD. The breadboard looked like the following:

The four digits display is the common cathode type, so segments must be sourced current from the output pins connected to the segments. Individual digits are selected by setting the common cathodes to zero volts. This is the reverse of the two digit displays used in the eight bit counter, as well as my laminator controller board, described previously. If I was doing this properly I would use transistor drivers on the cathode pins, but I’m being lazy so instead current that lights the LEDs flows in and out of the FPGA directly.

I’m now in the process of setting up my 6809 computer again so I can attempt to link it to the FPGA. Doing this will allow me to verify that the two parts, manufactured about 30 years apart, will be able to interoperate. Mirroring my experiments with the XC5972 CPLD, I will make the hex display into an output latch. I will also try hooking up a buzzer to the FPGA, and implement an output register for producing tones from the buzzer etc.

But that has to wait until I have setup the Xilinx tools on a new VirtualBox Windows image. Since I’ve not touched the 6809 in quite a while, I need to re-flash the original non-DMA controller design on the XC95108 CPLD and modify the 6809 monitor to work without the IO board attached. It seems like it’s been years since I touched the 6809 computer…

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