A working Single Board Computer

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Last Monday, April 28, the PCBs arrived. They only took a little over 72 hours door to door from Hong Kong. Pretty amazing service from DHL. And amazing service from Botech, who have done an excellent job making up my design. Here’s a picture of the five boards in their little wallet:
And here are pics of the bottom of one of the boards:
Monday evening I started the job of soldering up the board. My rough plan was to test as I went.
Before warming up the iron, I first did some basic continuity checks on the PCB, making sure at a minimum that the Vcc and ground rails weren’t shorted together somewhere.
Next I soldered up the power related components, including the USB and Molex connectors, power LED and resistor, and the fuse. Then I powered on the board and checked the power LED lit up, and checked for 5V at various places on the board.
The next job was to solder the buttons, halt/run switch, reset generator and CPU DIP socket. After that I checked the function of the buttons by measuring the voltage at the relevant CPU pins. Then I soldered the memory and DUART sockets.
After that it was time to tackle the “massive” 84 pin PLCC connector for the CPLD. I did this and the 10 pin IDC JTAG header before verifying that I could program the XC95108 “in circuit”. It was a big relief to see this work first time.
Next up was to solder on a few of the jumpers including the TTL serial lines, and the rest of the LEDs.
Then I needed to make a few small changes to the VHDL to make it generate constant values on the high address lines, the ones marked B4 to B0 in the circuit diagram, since the bank switching wasn’t yet implemented. The rest of the VHDL, to handle address decoding and other core things, was done a few weeks ago.
After all this was done, it was getting late and I thought about calling it a day. But I wanted to see if the computer would work. I wasn’t expecting it too, but I hooked up the USB serial adapter, fired up the terminal program, and powered up the board. Amazingly I saw my monitor prompt the first time!
I took a picture to mark the moment:
Here are some pics of the board fully populated and soldered. Well, I say fully populated but the decoupling capacitors are yet to be soldered. The board appears to work fine without them, but I will add them soon anyway. First the top:
And the bottom:
I really wish I had a way to remove the solder flux, since it really looks quite horrible. I must admit this is not my best soldering.
In the days since, I have tested and implemented additional functionality.
IDE interface in 8 bit mode: this worked first time, which is not much of a surprise since I had this working on breadboard last autumn,  Since I have soldered pin 20 to the 5V line, the Compact Flash adapter does not require extra power. Should I someday want to try out an IDE hard disk, I would need to remove pin 20 from the IDC plug. I doubt I will, since even a small CF provides more then enough storage. But it could be fun.
Bank switching: the HDL required is fairly simple. It requires the RAM Chip Select to be broken in two. If the low half is selected, then the five high bits of the physical address are forced to 00000 but if the high half is selected then the bank switching register should be output instead. Thus requests for addresses from 0x0000 to 0x3fff will always select the lowest 16KByte page, but requests for addresses from 0x4000 to 0x7fff will be mapped to one of the 31 other 16KByte banks. It is also possible to map this range to the same page as 0x0000 to 0x3fff is mapped to, but this does not seem very useful.
To make operation of the bank switching latch simpler then a write to a specific IO address, two commands have been added to the monitor:
  • b NN – switch to bank NN
  • B – show the current bank number

They are trivial enough; they just write and read the bank switching latch register address. But they save some typing. The following screenshot shows the monitor being used to switch bank after writing some data into the first few bytes of each selected bank. Finally the content of the first few bytes in each bank is shown:
Beeper: this was prototyped on the XC9572 in the breadboard so I didn’t expect any problems. A single register holds the period of the tone, but to yield a useful frequency the E clock line is first divided down by a 7 bit counter. It is then divided down by the sound period register, and assuming that register isn’t zero, the output line connected to the sounder matches the highest bit in the sound period counter. This makes it possible to output a tone at between about 15KHz and 61Hz.
The monitor has been modified to make use of the sounder by producing beeps at startup.
Once the VHDL is a bit better structured, and commented, I will upload it to github.
There’s a few outstanding issues to investigate before I get on to working on the I/O board.
The MAX232: for some reason hooking up a plain null modem cable isn’t working. I think the IC I’m using must be faulty as I have checked and double checked the circuit and it matches many other people’s examples as well as the datasheet. Since I don’t own an oscilloscope tracking this problem down could be awkward. I’ve ordered a bunch more MAX232s so I will soon find out.
The 16bit mode IDE is causing me some headaches. I need to create two latches in VHDL, one for reading and one for writing. Also the latch needs to get its value from the IDE when a read occurs on the actual IDE interface not when the latch itself is read. And likewise for writes.
One small quirk with in circuit updates of the CPLD bares a mention. While the IC is being programmed over JTAG, it seems that the IO pins are being driven low causing the EEPROM content to be corrupted, since the read/write pin is active low for writes. In the previous board I had a write protect jumper which could have been useful to tie the R/W line high while the CPLD is being programmed, but I left it off this design thinking I could use the programmable logic to implement write protect. But I forgot about the time the CPLD is programmed. It’s not a big problem; I just unsocket the EEPROM before I program the CPLD. Annoying but won’t be a problem once the VHDL is finalised and stops changing so often.
I have yet to extend the address decoding to deal with the eight “off board” chip selects, but that is simple. Nor have I done anything with the configuration jumpers. Those will probably be used to write protect sections of the EEPROM as initially decided, though I could alternatively make them simple monitor configuration registers and then a jumper could be used to set the active serial port or something similar.
Due to a quirk in the PCB layout software, it neglected to highlight a mistake with one of the pins on the expansion connector. The ungated (off the 6809) Read/Write line isn’t connected. This is because I made a typo in the schematic. I still have the Read and Write (gated through E) lines available, which is what 99% of peripheral chips require, but it is still annoying. But if I should require this line on the I/O board then I can borrow one of the 8 expansion Chip Selects by routing a copy of the Read/Write signal through it and reducing the number of Chip Selects down to 7.

Anyway, I am very happy with my progress the last few weeks. I look forward to working on the I/O board, something I hope to start soon by prototyping up elements on breadboard. Probably the first thing I will get working is the 65SPI…

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