So, it’s been a bit of a mixed bag this month with the 6809 computer. First of all, I have decided to do the SBC “properly” and use a single CPLD instead of two. With that goal in mind, I’ve ordered a few parts:
- XC9572 in PLCC84 (3 of)
- PLCC84 sockets (4 of)
Initially I wanted to buy some XC95108s. These have 108 registers, so can be used to create slightly more complex designs. But UTSource (my favorite Chinese eBay seller), although they were listed as being in stock didn’t actually have any. So I had to go for the more limited ’72 parts.
But then I had some good luck: a fellow user of the 6502.org forums, lordbubsy, had a spare XC95108 PLCC84 and a nice breakout PCB with socket available. In turn I’ve sent him a spare Xilinx USB JTAG programmer. So very shortly I should have more then enough CPLDs to last me including 3 x 44pin XC9572, 3 x 84 pin XC9572 and a 84 pin XC95108, along with plenty of PLCC sockets. Phew!
Using a single CPLD will save me a whole bunch of pins, and should allow me to create a fairly sophisticated custom IC design. I’ve started to code up what I described in my previous post, with the addition of a sound output line. This will be the most complicated part of the design. The purpose (other then for fun and learning) of the sound output is so that I can include a small sounder on the SBC PCB itself. I can then have the computer generate tones on booting, etc.
There are many approaches to tone generation in a simple micro like mine. The simplest is just to attach an output line (accessed through a latch) to a sounder. It’s then simple to, in software, toggle the line on and off at a reasonable speed (say 1KHz) to generate a tone. But much better then this is to use the system clock, and a programmed divider/counter to automatically toggle the output pin. That way you only need to write to a port once to generate a continuous tone at a particular frequency. Even better then this would be a system which uses a second register to hold a duration – the amount of time the tone should be played for. This is what I’ve started to implement, and have mostly working in prototype form. It requires quite a fair chunk of the resources available to a simple CPLD like the XC9572, since it has to include several counters and some comparators.
So a summary of the “features” for my “custom IC”:
- Address decoding:
- RAM, ROM, DUART and IDE outputs
- 8 expansion selects
- 8 address inputs (the high byte of the bus)
- READ, WRITE generation via E, Q and R/W inputs
- RESET generation
- IDE latch to fascilitate 16 bit IDE transfers
- RAM bank switching latch
- Interrupt routing:
- DUART and IDE on the SBC
- 4 expansion inputs
- General purpose button for, say, NMI generation
- ROM write-protect control via jumpers
- Sound output line
To facilitate the two latches, and the sound output, the device needs to receive the full databus and A0 (giving two registers per decoded device).
The circuit for the computer main board currently looks like the following:
I’ve made quite a bit of progress on the PCB, but it isn’t quite finished yet: